A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protection

Cheng Yen Lee, Tzu Ping Huang, Ke Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

研究成果: Conference contribution同行評審

摘要

This paper proposes a stacked digital low dropout (DLDO) array with three stacked groups to improve security and efficiency, consuming 1/3 of the input current in the prior art. The security is improved by two mechanisms. The advanced encryption standard (AES) engine can be one of point of loads (POLs) hidden in the deeper levels to minimize the disturbance from the AES to the input current. The other is the digital balanced interleave control (DBIC) receives random sources from internal leakage current frequency generator (LCFG) to generate randomly noise current to further hide the current interference caused by the AES. Due to DBIC and LCFG techniques, the correlation between input current and AES current is low to 0.006, which is 150 times lower than that of conventional DLDO.

原文English
主出版物標題2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面C322-C323
ISBN(電子)9784863487185
DOIs
出版狀態Published - 六月 2019
事件33rd Symposium on VLSI Circuits, VLSI Circuits 2019 - Kyoto, Japan
持續時間: 9 六月 201914 六月 2019

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2019-June

Conference

Conference33rd Symposium on VLSI Circuits, VLSI Circuits 2019
國家Japan
城市Kyoto
期間9/06/1914/06/19

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