A hierarchical analysis methodology for chip-level power delivery with realizable model reduction

Yu-Min Lee, C. Chung-Ping Chen

研究成果: Conference contribution同行評審

摘要

In this paper, we propose a novel hierarchical analysis methodology to facilitate efficient chip-level power fluctuation analysis. With extreme efficiency and simplicity, our design methodology first builds time-varying multiport Norton equivalent circuits in a row-by-row or block-by-block basis, followed by global analysis of the integrated reduced models. After generating the Norton equivalent sources at external ports, we apply realizable model order reduction technologies to further reduce the model. Since the elements of our reduced model are also RC devices, they are fully compatible with general circuit simulation engines. The experimental results demonstrate more than 4X speed up with the flat simulation while maintaining within 5% accuracy.

原文English
主出版物標題Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面614-618
頁數5
ISBN(電子)0780376595
DOIs
出版狀態Published - 1 一月 2003
事件Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
持續時間: 21 一月 200324 一月 2003

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
國家Japan
城市Kitakyushu
期間21/01/0324/01/03

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