The voltage-mode hysteretic converter is one of ripple-based regulators. The converter has the salient features of fast transient response, good conversion efficiency, and simple architecture. However, the major drawbacks include large voltage ripple caused by propagation delay path and excess overshoot voltage during the start-up period. This paper presents an overshoot suppression technique uses two-phase PMOS transistors to optimize the solution among the overshoot voltage, transistor size, and conversion efficiency. There exists a design trade-offs between start-up overshoot voltage and settling time. Results show that, with the proposed suppression technique, the overshoot voltage is reduced from 340mV to 74.4mV. However, the settling time is increased from 15.1us to 21.74 us.