A controllable low-power dual-port embedded SRAM for DSP processor

Hao I. Yang*, Ming Hung Chang, Tay Jyi Lin, Shih Hao Ou, Siang Sen Deng, Chih-Wei Liu, Wei Hwang

*Corresponding author for this work

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%.

原文English
主出版物標題17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
頁面27-30
頁數4
DOIs
出版狀態Published - 1 十二月 2007
事件17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan
持續時間: 3 十二月 20075 十二月 2007

出版系列

名字Records of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN(列印)1087-4852

Conference

Conference17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
國家Taiwan
城市Taipei
期間3/12/075/12/07

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