A compact DSP core with static floating-point unit & its microcode generation

Tay Jyi Lin*, Hung Yueh Lin, Chie Min Chao, Chih-Wei Liu, Chein Wei Jen

*Corresponding author for this work

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

The multimedia SoC usually integrates programmable digital signal processors (DSP) to accelerate data-intensive computations. But the DSP and the host processor (e.g. ARM) are both designed for standalone uses, and they must have overlapped functionalities and thus some redundant components. In this paper, we propose a compact DSP core for dual-core multimedia SoC and its complete software development tools. The DSP core contains a dataflow engine that is composed of off-the-shelf memory modules with limited ports, and we have investigated software techniques extensively to reduce the hardware complexity as the principles of VLIW processors. Moreover, the DSP is equipped with novel static floating-point units to emulate expensive floating-point DSP operations at low cost. In our experiments, this core has about thrice the performance (estimated in execution cycles) of Analog Devices ADSP-218x with similar computing resources. Our first prototype in the 0.35μm CMOS technology operates at 100MHz and consumes 122mW power. The core size is 2.8mm2 including an embedded DMA controller and the AMBA AHB interface.

原文English
主出版物標題Proceedings of the 2004 ACM Great Lakes Symposium on VLSI, GLSVLSI 2004
主出版物子標題VLSI in the Nanometer Era
頁面57-60
頁數4
DOIs
出版狀態Published - 28 六月 2004
事件Proceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era - Boston, MA, United States
持續時間: 26 四月 200428 四月 2004

出版系列

名字Proceedings of the ACM Great Lakes Symposium on VLSI

Conference

ConferenceProceedings of the 2004 ACM Great lakes Symposium on VLSI, GLSVLSI 2004: VLSI in the Nanometer Era
國家United States
城市Boston, MA
期間26/04/0428/04/04

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