A CMOS 33-mW 100-MHz 80-dB SFDR Sample-and-Hold Amplifier

Cheng Chung Hsu*, Jieh-Tsorng Wu

*Corresponding author for this work

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the stringent performance requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25μm CMOS technology, the SHA achieves 80 dB spurious-free dynamic range (SFDR) for a 1.8 Vpp output at 100 MHz Nyquist sampling rate. The SHA occupies a die area of 0.35 mm2 and dissipates 33 mW from a single 2.5 V supply.

原文English
頁(從 - 到)2122-2128
頁數7
期刊IEICE Transactions on Electronics
E86-C
發行號10
DOIs
出版狀態Published - 1 一月 2003

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