A capacitorless double-gate DRAM cell

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

研究成果: Letter同行評審

64 引文 斯高帕斯(Scopus)

摘要

A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off-state leakage and disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dVT)/(dVBS)) transforms small gains of body potential into increased drain current. MEDICI simulations for 85°C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies.

原文English
頁(從 - 到)345-347
頁數3
期刊IEEE Electron Device Letters
23
發行號6
DOIs
出版狀態Published - 1 六月 2002

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