A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications

Chang Hung Tsai, Tung Yu Wu, Shu Yu Hsu, Chia Ching Chu, Fang Ju Ku, Ying Siou Laio, Chih Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

A data-driven machine learning processor (D2MLP) with MIMD architecture is designed for big data analysis. Adopting the configurable counting engine array with 3-layer dimension merging, the D2MLP processes maximal 1-128/1024 dimensional data with parallel 64/8 queries in learning stage. Implement in 90nm CMOS technology, the D2MLP achieves 219.9x and 8.2x faster processing time than CPU and GPGPU, respectively. In application phase, maximal 22.7k 128-class classifications/s are performed with the learned density model. Operated at 1.0V and 165MHz, the D2MLP demonstrates an energy-efficient solution for learning and classification with 7.11mJ/Gb/query and 2.3μJ/classification, respectively.

原文English
主出版物標題2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)9781479933273
DOIs
出版狀態Published - 1 一月 2014
事件28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States
持續時間: 10 六月 201413 六月 2014

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference28th IEEE Symposium on VLSI Circuits, VLSIC 2014
國家United States
城市Honolulu, HI
期間10/06/1413/06/14

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