A 70nW, 0.3V temperature compensation voltage reference consisting of subthreshold MOSFETs in 65nm CMOS technology

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Being operated with 0.3V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated voltage reference circuit is proposed with subthreshold transistors and native nMOS. The reference drain current provided by the gate voltage of a subthreshold nMOS output transistor is nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated voltage reference circuit functions well with the output voltage Vref of 168 mV at room temperature as no extra laser trimming is needed after fabrication. The total power consumption is about 70nW. With the VDD power supply of 0.3V, the temperature coefficient (TC) of voltage reference circuit is 105 ppm/°C as temperature varies from -20°C to 100°C. The chip size of the fabricated bandgap reference circuit is 0.0053mm2.

原文English
主出版物標題2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467394987
DOIs
出版狀態Published - 31 五月 2016
事件2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
持續時間: 25 四月 201627 四月 2016

出版系列

名字2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Conference

Conference2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
國家Taiwan
城市Hsinchu
期間25/04/1627/04/16

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