A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

Jongsun Kim*, Ingrid Verbauwhede, Mau-Chung Chang

*Corresponding author for this work

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

This paper describes a low-power synchronous pulsed signaling scheme on a fully ac coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifler at 500 MHz. The fully ac coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-μm 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330 × 85 μm2.

原文English
頁(從 - 到)1331-1340
頁數10
期刊IEEE Journal of Solid-State Circuits
40
發行號6
DOIs
出版狀態Published - 1 六月 2005

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