A 50 to 70 GHz power amplifier using 90 nm CMOS technology

Jing Lin Kuo; Zuo-Min Tsai; Kun You Lin; Huei Wang

doi:10.1109/LMWC.2008.2008603

A 50 to 70 GHz power amplifier using 90 nm CMOS technology

Jing Lin Kuo^*, Zuo-Min Tsai , Kun You Lin, Huei Wang

^*Corresponding author for this work

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研究成果: Article › 同行評審

39 引文斯高帕斯（Scopus）

摘要

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V _DD is biased at 3 V, it exhibits P_sat of 18 dBm, P _{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 × 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.

原文	English
文章編號	4729665
頁（從 - 到）	45-47
頁數	3
期刊	IEEE Microwave and Wireless Components Letters
卷	19
發行號	1
DOIs	https://doi.org/10.1109/LMWC.2008.2008603
出版狀態	Published - 1 一月 2009

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abstract = "A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured Psat of 13.8 dBm, P1 dB of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under VDD biased at 1.8 V. When V DD is biased at 3 V, it exhibits Psat of 18 dBm, P 1 dB of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 × 0.5 mm2. To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.",

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