A 40mW 3.5kΩ 3Gb/s CMOS differential transimpedance amplifier using negative-impedance compensation

Chia-Ming Tsai*, Wen Tsao Chen

*Corresponding author for this work

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

Combining the self-compensated topology with the negative-impedance- compensation technique, a differential TIA with enlarged input-capacitance tolerances is designed in a 0.18μm CMOS technology. The DR is measured to be >20dB without using any gain control. The complete TIA IC consumes 40mW from a 1.8V supply.

原文English
主出版物標題2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs
出版狀態Published - 27 九月 2007
事件54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
持續時間: 11 二月 200715 二月 2007

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN(列印)0193-6530

Conference

Conference54th IEEE International Solid-State Circuits Conference, ISSCC 2007
國家United States
城市San Francisco, CA
期間11/02/0715/02/07

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  • 引用此

    Tsai, C-M., & Chen, W. T. (2007). A 40mW 3.5kΩ 3Gb/s CMOS differential transimpedance amplifier using negative-impedance compensation. 於 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers [4242260] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2007.373583