A 40-mW 7-bit 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communications

I. Ning Ku*, Zhiwei Xu, Yen-Cheng Kuan, Yen Hsiang Wang, Mau-Chung Chang

*Corresponding author for this work

研究成果: Article同行評審

20 引文 斯高帕斯(Scopus)

摘要

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm 2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC.

原文English
文章編號6212475
頁(從 - 到)1854-1865
頁數12
期刊IEEE Journal of Solid-State Circuits
47
發行號8
DOIs
出版狀態Published - 13 六月 2012

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