A 40 mW 3 Gb/s self-compensated differential transimpedance amplifier with enlarged input capacitance tolerance in 0.18 μm CMOS technology

Chia-Ming Tsai*

*Corresponding author for this work

研究成果: Article同行評審

5 引文 斯高帕斯(Scopus)

摘要

By combining an appropriate differential-sensing scheme with the bootstrapping technique, this paper presents a self-compensated design topology which is shown to be effective at reducing the loading effects due to the photodiode and the ESD protection circuit at the differential inputs. The built-in offset creation technique is introduced to overcome voltage headroom limitation. Furthermore, the negative impedance compensation is employed to enhance the gain-bandwidth product. The IC is shown to be tolerant of ESD protection circuit with 0.5 pF equivalent capacitance at the differential inputs. While connected to an InGaAs PIN photodiode exhibiting 0.8 pF equivalent capacitance, the implemented IC has achieved a differential transimpedance gain of 3.5 kΩ and a -3 dB bandwidth of 1.72 GHz. At a data rate of 3 Gb/s, the measured dynamic range is from -20 dBm to +0 dBm at a bit-error rate of 10-12 with a 231-1 pseudorandom test pattern. The negative impedance compensation is shown to achieve enhancement factors of 4.5 dB and 520%, respectively, for transimpedance gain and -3 dB bandwidth. The IC totally consumes 40 mW from a 1.8 V supply.

原文English
文章編號10
頁(從 - 到)2671-2677
頁數7
期刊IEEE Journal of Solid-State Circuits
44
發行號10
DOIs
出版狀態Published - 1 十月 2009

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