A 350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

Hiroyuki Hara*, Yasuhiro Sugimoto, Makoto Noda, Tetsu Nagamatsu, Yoshinori Watanabe, Hiroshi Iwai, Yoichirou Niitsu, Gen Sasaki, Kenji Maeguchi

*Corresponding author for this work

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

A BiCMOS gate array with the gate delay of 350 ps has been realized by 0.8 μm BiCMOS technology. Minimum gate delay and minimum cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5 μm pure CMOS gate array. Cell area increase is minimized to only 25 % compared with a 0.8 μm pure CMOS cell. I/O cells can interface with CMOS, TIL and ECL chips at the same time with a single supply voltage of 5 V.

原文English
文章編號5726179
頁(從 - 到)8.5.1-8.5.4
期刊Proceedings of the Custom Integrated Circuits Conference
DOIs
出版狀態Published - 1989
事件11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States
持續時間: 15 五月 198918 五月 1989

指紋 深入研究「A 350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure」主題。共同形成了獨特的指紋。

引用此