A 3.33Gb/s (1200,720) low-density parity check code decoder

Chien Ching Lin; Kai Li Lin; Hsie-Chia Chang; Chen-Yi Lee

doi:10.1109/ESSCIR.2005.1541597

A 3.33Gb/s (1200,720) low-density parity check code decoder

Chien Ching Lin^*, Kai Li Lin, Hsie-Chia Chang, Chen-Yi Lee

^*Corresponding author for this work

電子工程學系

研究成果: Conference contribution › 同行評審

34 引文斯高帕斯（Scopus）

摘要

In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm² 0.18μm silicon area. The other 0.13μm chip with the 10.24mm² core can further reach a 5.92Gb/s data rate under 1.02V supply.

原文	English
主出版物標題	Proceedings of ESSCIRC 2005
主出版物子標題	31st European Solid-State Circuits Conference
頁面	211-214
頁數	4
DOIs	https://doi.org/10.1109/ESSCIR.2005.1541597
出版狀態	Published - 1 十二月 2005
事件	ESSCIRC 2005: 31st European Solid-State Circuits Conference - Grenoble, France 持續時間: 12 九月 2005 → 16 九月 2005

出版系列

名字	Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Conference

Conference	ESSCIRC 2005: 31st European Solid-State Circuits Conference
國家	France
城市	Grenoble
期間	12/09/05 → 16/09/05

存取文件

10.1109/ESSCIR.2005.1541597

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引用此

@inproceedings{3aa0570313b84d458de248edc24d6227,

title = "A 3.33Gb/s (1200,720) low-density parity check code decoder",

abstract = "In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm2 0.18μm silicon area. The other 0.13μm chip with the 10.24mm2 core can further reach a 5.92Gb/s data rate under 1.02V supply.",

author = "Lin, {Chien Ching} and Lin, {Kai Li} and Hsie-Chia Chang and Chen-Yi Lee",

year = "2005",

month = dec,

day = "1",

doi = "10.1109/ESSCIR.2005.1541597",

language = "English",

isbn = "0780392051",

series = "Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference",

pages = "211--214",

booktitle = "Proceedings of ESSCIRC 2005",

note = "null ; Conference date: 12-09-2005 Through 16-09-2005",

}

Lin, CC, Lin, KL, Chang, H-C & Lee, C-Y 2005, A 3.33Gb/s (1200,720) low-density parity check code decoder. 於 Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference., 1541597, Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference, 頁 211-214, ESSCIRC 2005: 31st European Solid-State Circuits Conference, Grenoble, France, 12/09/05. https://doi.org/10.1109/ESSCIR.2005.1541597

TY - GEN

T1 - A 3.33Gb/s (1200,720) low-density parity check code decoder

AU - Lin, Chien Ching

AU - Lin, Kai Li

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

PY - 2005/12/1

Y1 - 2005/12/1

N2 - In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm2 0.18μm silicon area. The other 0.13μm chip with the 10.24mm2 core can further reach a 5.92Gb/s data rate under 1.02V supply.

AB - In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm2 0.18μm silicon area. The other 0.13μm chip with the 10.24mm2 core can further reach a 5.92Gb/s data rate under 1.02V supply.

UR - http://www.scopus.com/inward/record.url?scp=33749160113&partnerID=8YFLogxK

U2 - 10.1109/ESSCIR.2005.1541597

DO - 10.1109/ESSCIR.2005.1541597

M3 - Conference contribution

AN - SCOPUS:33749160113

SN - 0780392051

SN - 9780780392052

T3 - Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

SP - 211

EP - 214

BT - Proceedings of ESSCIRC 2005

Y2 - 12 September 2005 through 16 September 2005

ER -