A 3.33Gb/s (1200,720) low-density parity check code decoder

Chien Ching Lin*, Kai Li Lin, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

研究成果: Conference contribution同行評審

34 引文 斯高帕斯(Scopus)

摘要

In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm2 0.18μm silicon area. The other 0.13μm chip with the 10.24mm2 core can further reach a 5.92Gb/s data rate under 1.02V supply.

原文English
主出版物標題Proceedings of ESSCIRC 2005
主出版物子標題31st European Solid-State Circuits Conference
頁面211-214
頁數4
DOIs
出版狀態Published - 1 十二月 2005
事件ESSCIRC 2005: 31st European Solid-State Circuits Conference - Grenoble, France
持續時間: 12 九月 200516 九月 2005

出版系列

名字Proceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2005: 31st European Solid-State Circuits Conference
國家France
城市Grenoble
期間12/09/0516/09/05

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