A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter with Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS

Boyu Hu*, Yanghyo Kim, Rulin Huang, Yuan Du, Mau-Chung Chang

*Corresponding author for this work

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.

原文English
文章編號8476164
頁(從 - 到)1056-1058
頁數3
期刊IEEE Microwave and Wireless Components Letters
28
發行號11
DOIs
出版狀態Published - 1 十一月 2018

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