A 2GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18μm CMOS. Three cross-connected and pre-distorted reference voltages improve the averaging performance. Circuit techniques enabling an SNDR of 30dB at Nyquist input frequency and a FOM of 3.5pJ per conversion step are discussed, and experimental results validating the simulated performance metrics are presented.
|期刊||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|出版狀態||Published - 23 七月 2003|
|事件||2003 Digest of Technical Papers - , United States|
持續時間: 9 二月 2003 → 13 二月 2003