A 2GS/s 6b ADC in 0.18μm CMOS

Xicheng Jiang*, Zhengyu Wang, Mau-Chung Chang

*Corresponding author for this work

研究成果: Conference article同行評審

62 引文 斯高帕斯(Scopus)

摘要

A 2GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18μm CMOS. Three cross-connected and pre-distorted reference voltages improve the averaging performance. Circuit techniques enabling an SNDR of 30dB at Nyquist input frequency and a FOM of 3.5pJ per conversion step are discussed, and experimental results validating the simulated performance metrics are presented.

原文English
期刊Digest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
出版狀態Published - 23 七月 2003
事件2003 Digest of Technical Papers - , United States
持續時間: 9 二月 200313 二月 2003

指紋 深入研究「A 2GS/s 6b ADC in 0.18μm CMOS」主題。共同形成了獨特的指紋。

引用此