A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

Po Chun Liu*, Ju Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

研究成果: Conference contribution同行評審

8 引文 斯高帕斯(Scopus)

摘要

This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.

原文English
主出版物標題ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference
頁面71-74
頁數4
DOIs
出版狀態Published - 12 十二月 2011
事件37th European Solid-State Circuits Conference, ESSCIRC 2011 - Helsinki, Finland
持續時間: 12 九月 201116 九月 2011

出版系列

名字European Solid-State Circuits Conference
ISSN(列印)1930-8833

Conference

Conference37th European Solid-State Circuits Conference, ESSCIRC 2011
國家Finland
城市Helsinki
期間12/09/1116/09/11

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