A 2.56 Gb/s Soft RS (255, 239) decoder chip for optical communication systems

Yi Min Lin, Chih Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at 10-4 codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.

原文English
文章編號6731597
頁(從 - 到)2110-2118
頁數9
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
61
發行號7
DOIs
出版狀態Published - 1 一月 2014

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