A 24 GHz Low-power and High-gain Low-noise Amplifier Using 0.18 mu m CMOS Technology for FMCW Radar Applications

Chun Yi Lin, Ming Wei Lin, Ching Piao Liang, Shyh-Jong Chung

研究成果: Conference contribution

摘要

In this paper, a low power and high gain low-noise amplifier (LNA) is presented for 24 GHz FMCW radar applications fabricated in a 0.18 mu m RF CMOS process. The proposed LNA is with the characteristics of the source inductive degeneration type, the current reuse technique, and the invariance of current density in CMOS process. The proposed LNA with a compact size has a gain of 18.95 dB and a noise figure of 5.8 dB, while consuming 11.3 mW. The measured input 1-dB compression point (IP1 dB) and an input third-order intercept point (IIP3) are -26 dBm and -16.5 dBm, respectively.
原文English
主出版物標題Progress in Electromagnetics Research Symposium
發行者Electromagnetics Academy
頁面892-896
頁數5
出版狀態Published - 2012

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    Lin, C. Y., Lin, M. W., Liang, C. P., & Chung, S-J. (2012). A 24 GHz Low-power and High-gain Low-noise Amplifier Using 0.18 mu m CMOS Technology for FMCW Radar Applications. 於 Progress in Electromagnetics Research Symposium (頁 892-896). Electromagnetics Academy.