A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery

Yuan Sheng Lee, Wei-Zen Chen

研究成果: Conference contribution同行評審

摘要

A single chip optical receiver comprising of a fontend amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 231-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10-12 (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm2. It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.

原文English
主出版物標題2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781538648810
DOIs
出版狀態Published - 26 四月 2018
事件2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
持續時間: 27 五月 201830 五月 2018

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
2018-May
ISSN(列印)0271-4310

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
國家Italy
城市Florence
期間27/05/1830/05/18

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