A 1.7mW all digital phase-locked loop with new gain generator and low power DCO

Tzu Chiang Chao*, Wei Hwang

*Corresponding author for this work

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper, a new architecture and algorithm for all digital phase-locked loop (ADPLL) is proposed. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator (DCO) structure for low power, small area is presented and its frequency range is from 200 MHz to 750 MHz with a supply voltage 1.2v. The total power consumption of ADPLL is 1.7mW. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption. This ADPLL is designed and implemented by TSMCs 0.13um CMOS technology.

原文English
主出版物標題ISCAS 2006
主出版物子標題2006 IEEE International Symposium on Circuits and Systems, Proceedings
頁面4867-4870
頁數4
DOIs
出版狀態Published - 1 十二月 2006
事件ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
持續時間: 21 五月 200624 五月 2006

出版系列

名字Proceedings - IEEE International Symposium on Circuits and Systems
ISSN(列印)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
國家Greece
城市Kos
期間21/05/0624/05/06

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