A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology

Wei-Zen Chen*, Tai You Lu, Yan Ting Wang, Jhong Ting Jian, Yi Hung Yang, Guo Wei Huang, Wen De Liu, Chih Hua Hsiao, Shu Yu Lin, Jung Yen Liao

*Corresponding author for this work

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm 2. This chip drains 24mW from a 1.2V power supply.

原文English
主出版物標題2012 Symposium on VLSI Circuits, VLSIC 2012
頁面12-13
頁數2
DOIs
出版狀態Published - 28 九月 2012
事件2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
持續時間: 13 六月 201215 六月 2012

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2012 Symposium on VLSI Circuits, VLSIC 2012
國家United States
城市Honolulu, HI
期間13/06/1215/06/12

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