A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su, Wei-Zen Chen, Pei Si Wu, Yu Hsian Chen, Chao Cheng Lee, Shyh-Jye Jou

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI pp input data jitter, the recovered clock jitter at 2GHz is 2.94ps rms . The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm 2 .

原文English
主出版物標題Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)9781467361460
DOIs
出版狀態Published - 7 十一月 2013
事件35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
持續時間: 22 九月 201325 九月 2013

出版系列

名字Proceedings of the Custom Integrated Circuits Conference
ISSN(列印)0886-5930

Conference

Conference35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
國家United States
城市San Jose, CA
期間22/09/1325/09/13

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