A 10-bit area-efficient SAR ADC with re-usable capacitive array

Chung Yi Li, Chih Wen Lu*, Hao Tsun Chao, Chin Hsia

*Corresponding author for this work

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.

原文English
主出版物標題2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012
DOIs
出版狀態Published - 2012
事件2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012 - Taipei, Taiwan
持續時間: 24 八月 201226 八月 2012

出版系列

名字Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID
ISSN(列印)2163-5048
ISSN(電子)2163-5056

Conference

Conference2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012
國家Taiwan
城市Taipei
期間24/08/1226/08/12

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  • 引用此

    Li, C. Y., Lu, C. W., Chao, H. T., & Hsia, C. (2012). A 10-bit area-efficient SAR ADC with re-usable capacitive array. 於 2012 International Conference on Anti-Counterfeiting, Security and Identification, ASID 2012 [6325302] (Proceedings of the International Conference on Anti-Counterfeiting, Security and Identification, ASID). https://doi.org/10.1109/ICASID.2012.6325302