In this paper, an area-efficient successive approximation register (SAR) analog-to-digital converter (ADC) with a dithering Vref is proposed. It reuses the capacitive array with the reconfiguration of Vref to Vref ± ΔV for reducing dramatically the ADC's area. The 2n resolution is achieved by the n bit SAR-ADC. To verify the proposed scheme, the proposed SAR ADC is implemented in a TSMC 0.18 μm 1P6M CMOS process with a supply voltage of 1.8V. The simulation results show that the capacitor area is reduced by 96% compared with the conventional 10-bit SAR-ADC. The ENOB of the proposed architecture is 9.767 bit when operating at 14MS/s.