A 1 v 175 μw 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques

Sheng Hui Liao, Jieh-Tsorng Wu

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial integration cycle. Operating at 5 MS/s sampling rate, this chip consumes 175 μW from a 1 V supply. Assuming a 25 kHz signal bandwidth, it achieves 96.1 dB SNR, 94.6 dB SNDR, and 98.5 dB DR. Its active area is 113 × 0 34 mm2.

原文English
主出版物標題2018 IEEE Custom Integrated Circuits Conference, CICC 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1-4
頁數4
ISBN(電子)9781538624838
DOIs
出版狀態Published - 9 五月 2018
事件2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States
持續時間: 8 四月 201811 四月 2018

出版系列

名字2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Conference

Conference2018 IEEE Custom Integrated Circuits Conference, CICC 2018
國家United States
城市San Diego
期間8/04/1811/04/18

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