A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 μW from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 × 0.34mm2.