A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

Chao Chang Chiu; Po Hsien Huang; Moris Lin; Ke-Horng Chen; Ying Hsi Lin; Tsung Yen Tsai; Chen Chih Huang; Chao Cheng Lee

A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

Chao Chang Chiu, Po Hsien Huang, Moris Lin, Ke-Horng Chen, Ying Hsi Lin, Tsung Yen Tsai, Chen Chih Huang, Chao Cheng Lee

電機工程學系

研究成果: Conference contribution › 同行評審

14 引文斯高帕斯（Scopus）

摘要

Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.

原文	English
主出版物標題	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
出版狀態	Published - 17 九月 2013
事件	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan 持續時間: 12 六月 2013 → 14 六月 2013

出版系列

名字	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2013 Symposium on VLSI Circuits, VLSIC 2013
國家	Japan
城市	Kyoto
期間	12/06/13 → 14/06/13

存取文件

Link to publication in Scopus

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引用此

Chiu, C. C., Huang, P. H., Lin, M., Chen, K-H., Lin, Y. H., Tsai, T. Y., Huang, C. C., & Lee, C. C. (2013). A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement. 於 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers [6578649] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Chiu, Chao Chang ; Huang, Po Hsien ; Lin, Moris ; Chen, Ke-Horng ; Lin, Ying Hsi ; Tsai, Tsung Yen ; Huang, Chen Chih ; Lee, Chao Cheng. / A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement. 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{7cd7ed831513493a9a801e4d11cc417d,

title = "A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement",

abstract = "Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.",

author = "Chiu, {Chao Chang} and Huang, {Po Hsien} and Moris Lin and Ke-Horng Chen and Lin, {Ying Hsi} and Tsai, {Tsung Yen} and Huang, {Chen Chih} and Lee, {Chao Cheng}",

year = "2013",

month = sep,

day = "17",

language = "English",

isbn = "9784863483484",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

booktitle = "2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers",

note = "null ; Conference date: 12-06-2013 Through 14-06-2013",

}

Chiu, CC, Huang, PH, Lin, M, Chen, K-H, Lin, YH, Tsai, TY, Huang, CC & Lee, CC 2013, A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement. 於 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578649, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 12/06/13.

A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement. / Chiu, Chao Chang; Huang, Po Hsien; Lin, Moris; Chen, Ke-Horng; Lin, Ying Hsi; Tsai, Tsung Yen; Huang, Chen Chih; Lee, Chao Cheng.

2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. 6578649 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

AU - Chiu, Chao Chang

AU - Huang, Po Hsien

AU - Lin, Moris

AU - Chen, Ke-Horng

AU - Lin, Ying Hsi

AU - Tsai, Tsung Yen

AU - Huang, Chen Chih

AU - Lee, Chao Cheng

PY - 2013/9/17

Y1 - 2013/9/17

N2 - Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.

AB - Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.

UR - http://www.scopus.com/inward/record.url?scp=84883782007&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84883782007

SN - 9784863483484

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers

Y2 - 12 June 2013 through 14 June 2013

ER -