A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

Chao Chang Chiu, Po Hsien Huang, Moris Lin, Ke-Horng Chen, Ying Hsi Lin, Tsung Yen Tsai, Chen Chih Huang, Chao Cheng Lee

研究成果: Conference contribution同行評審

14 引文 斯高帕斯(Scopus)

摘要

Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.

原文English
主出版物標題2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
出版狀態Published - 17 九月 2013
事件2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
持續時間: 12 六月 201314 六月 2013

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2013 Symposium on VLSI Circuits, VLSIC 2013
國家Japan
城市Kyoto
期間12/06/1314/06/13

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