A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter

Hung Kai Chen, Wei-Zen Chen, Zhiyuan Ren

研究成果: Conference contribution

摘要

This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time ΔΣ analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 μW. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm2.

原文English
主出版物標題Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
編輯Junyan Ren, Ting-Ao Tang, Fan Ye, Huihua Yu
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781479984831
DOIs
出版狀態Published - 21 七月 2016
事件11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China
持續時間: 3 十一月 20156 十一月 2015

出版系列

名字Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

Conference

Conference11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
國家China
城市Chengdu
期間3/11/156/11/15

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  • 引用此

    Chen, H. K., Chen, W-Z., & Ren, Z. (2016). A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter. 於 J. Ren, T-A. Tang, F. Ye, & H. Yu (編輯), Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7517109] (Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7517109