A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

Yao Chia Liu, Wei-Zen Chen, Mao Hsuan Chou, Tsung Hsien Tsai, Yen Wei Lee, Min Shueh Yuan

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

A 0.1-3 GHz, cell-based, fractional-N ADPLL with ΔΣ noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um × 240um.

原文English
主出版物標題Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)9781467361460
DOIs
出版狀態Published - 7 十一月 2013
事件35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
持續時間: 22 九月 201325 九月 2013

出版系列

名字Proceedings of the Custom Integrated Circuits Conference
ISSN(列印)0886-5930

Conference

Conference35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
國家United States
城市San Jose, CA
期間22/09/1325/09/13

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