80nm SOI CMOS parameter extraction for BSIMPD

K. Goto*, Pin Su, Y. Tagawa, T. Sugii, Chen-Ming Hu

*Corresponding author for this work

研究成果: Paper

2 引文 斯高帕斯(Scopus)

摘要

A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.

原文English
頁面55-56
頁數2
出版狀態Published - 1 一月 2001
事件2001 IEEE International SOI Conference - Durango, CO, United States
持續時間: 1 十月 20014 十月 2001

Conference

Conference2001 IEEE International SOI Conference
國家United States
城市Durango, CO
期間1/10/014/10/01

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  • 引用此

    Goto, K., Su, P., Tagawa, Y., Sugii, T., & Hu, C-M. (2001). 80nm SOI CMOS parameter extraction for BSIMPD. 55-56. 論文發表於 2001 IEEE International SOI Conference, Durango, CO, United States.