A simple parameter extraction flow and successful simulation results using 130 nm CMOS technology were analyzed. The thermal resistance verification was also performed using DC drain current on body bias dependence. Simulation results in the small gate length down to 79 nm using BSIMPD model.
|出版狀態||Published - 1 一月 2001|
|事件||2001 IEEE International SOI Conference - Durango, CO, United States|
持續時間: 1 十月 2001 → 4 十月 2001
|Conference||2001 IEEE International SOI Conference|
|期間||1/10/01 → 4/10/01|