55-mW 300-MHz analog-digital converters using digital VLSI technology

P. Sutardja*, D. D. Tang, J. Altieri, L. E. Thon, G. Coleman, S. Subbanna, J. Y.C. Sun

*Corresponding author for this work

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

A very high speed analog-digital converter (ADC) has been designed and fabricated using a 3.6-V, 0.8-micron and a 2.5-V, 0.5-micron digital CMOS technology. This converter is intended for the evaluation of the potential of scaled CMOS technologies for analog application. This article describes the design issues and the performance of the ADC fabricated in two generations of CMOS.

原文English
頁面68-69
頁數2
出版狀態Published - 1995
事件Proceedings of the 1995 IEEE Symposium on Low Power Electronics - San Jose, CA, USA
持續時間: 9 十月 199511 十月 1995

Conference

ConferenceProceedings of the 1995 IEEE Symposium on Low Power Electronics
城市San Jose, CA, USA
期間9/10/9511/10/95

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