3D-TCAD simulation study of the novel T-FinFET structure for sub-14nm metal-oxide-semiconductor field-effect transistor

Chen Han Chou, Chung Chun Hsu, Steve S. Chung, Chao Hsin Chien

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

We propose a novel device structure, namely T-FinFET, for sub-14nm MOSFET with using lighter anti punch through (APT) implant. According to 3D TCAD simulation, the T-FinFET is found to posses many advantages over the normal FinFET, such as better short channel effect (SCE) and drain induced barrier lowering (DIBL), having smaller S/D capacitance and junction leakage and fewer masks. Compared to gate-all-around (GAA) structure, the T-FinFET also has compatible electrical performance. All these features are obtained by depositing a self-aligned (SA) oxide after recessing the Si fin in the S/D region. It can be applied to Ge and III-V MOSFETs for suppressing the SCEs and S/D leakage, arising from higher permittivity and lower band gap than Si.

原文English
主出版物標題2015 Silicon Nanoelectronics Workshop, SNW 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9784863485389
出版狀態Published - 24 九月 2015
事件Silicon Nanoelectronics Workshop, SNW 2015 - Kyoto, Japan
持續時間: 14 六月 201515 六月 2015

出版系列

名字2015 Silicon Nanoelectronics Workshop, SNW 2015

Conference

ConferenceSilicon Nanoelectronics Workshop, SNW 2015
國家Japan
城市Kyoto
期間14/06/1515/06/15

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