20 Gbit/s AIGaAs/GaAs HBT decision circuit IC

G. Runge, J. L. Gimlett, R. B. Nubling, K. C. Wang, Mau-Chung Chang, R. L. Pierson, P. M. Asbeck

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

An experimental 20 Gbit/s decision circuit IC based on AlGaAs/GaAs HBTs has been implemented, which features a differential input sensitivity of 80 mV peak to peak and a phase margin of 292° at the SONET STS-192 rate of 9·95 Gbit/s. The IC nominally dissipates 870 mW of power, but may be operated up to 10 Gbit/s with a power dissipation of 450 mW. The circuit was fabricated in a high current gain baseline HBT technology, and occupies an area of 1·15 × 1 mm2.

原文English
頁(從 - 到)2376-2378
頁數3
期刊Electronics Letters
27
發行號25
DOIs
出版狀態Published - 5 十二月 1991

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