160 GHz parametric passive frequency doubler in CMOS 180nm technology

Beng Meng Chen, Zuo-Min Tsai

研究成果: Conference contribution同行評審

摘要

A parametric CMOS passive frequency doubler is reported in this paper. The circuit is implemented in 180 nm CMOS but oses a conservative 0.5um gate length and produces an output between 150GHz and 162 GHz with a minimum measured conversion loss of 19.15 dB. The maximum output power is -26.9 dBm by -4.25dBm input power. The proposed design series a transmission line at the transistor source and series a 500 Ohms resistance at the transistor body in order to improve the performance.

原文English
主出版物標題2015 International Workshop on Electromagnetics
主出版物子標題Applications and Student Innovation Competition, iWEM 2015
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467369527
DOIs
出版狀態Published - 23 十二月 2015
事件International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015 - Hsin-Chu, Taiwan
持續時間: 16 十一月 201518 十一月 2015

出版系列

名字2015 International Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015

Conference

ConferenceInternational Workshop on Electromagnetics: Applications and Student Innovation Competition, iWEM 2015
國家Taiwan
城市Hsin-Chu
期間16/11/1518/11/15

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