1.2V and 8.6mW CMOS differential receiver front-end with 24dB gain and -11dBm IRCP

D. Huang*, R. Wong, C. Chien, Mau-Chung Chang

*Corresponding author for this work

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

A 60GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24dB without buffer amplifier), high linearity (-11dBm input referred P 1dB compression point, or IRCP), low power dissipation (4.3mW/arm) and small die area (0.022mm 2 ).

原文English
頁(從 - 到)1449-1450
頁數2
期刊Electronics Letters
42
發行號25
DOIs
出版狀態Published - 20 十二月 2006

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