120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs

Hsiang An Yang, Chao Chang Chiu, Shin Chi Lai, Jui Lung Chen, Chih Wei Chang, Che Hao Meng, Ke-Horng Chen, Chin Long Wey, Ying Hsi Lin, Chao Cheng Lee, Jian Ru Lin, Tsung Yen Tsai, Hsin Yu Luo

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

High power density is a key point that power converters endeavor to pursue. However, it is rare that gate driver of power converter can switch under high supply voltage with a fast operation frequency. In this paper, a half-bridge driver with the slew rate enhancement (SRE) technique is proposed and its switching frequency can be increased to 25MHz under a 700V supply voltage. Besides, the proposed high voltage clamping circuit ensures all circuits operating in a safe region without any overvoltage problems in the bootstrap operation. With specifically developed high voltage high speed (HVHS) process, high-side and low-side circuits can be well shielded by the isolation well which is embedded in the level shifter device to minimize chip size.

原文English
主出版物標題ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
編輯Franz Dielacher, Wolfgang Pribyl, Gernot Hueber
發行者IEEE Computer Society
頁面291-294
頁數4
ISBN(電子)9781467374705
DOIs
出版狀態Published - 30 十月 2015
事件41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
持續時間: 14 九月 201518 九月 2015

出版系列

名字European Solid-State Circuits Conference
2015-October
ISSN(列印)1930-8833

Conference

Conference41st European Solid-State Circuits Conference, ESSCIRC 2015
國家Austria
城市Graz
期間14/09/1518/09/15

指紋 深入研究「120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs」主題。共同形成了獨特的指紋。

引用此