1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology

Tien Y. Lo*, Chung-Chih Hung

*Corresponding author for this work

研究成果: Conference article同行評審

6 引文 斯高帕斯(Scopus)

摘要

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 μW. Simulation results demonstrate the agreement with theoretical analyses.

原文English
文章編號4253507
頁(從 - 到)3792-3795
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 27 九月 2007
事件2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
持續時間: 27 五月 200730 五月 2007

指紋 深入研究「1-V linear CMOS transconductor with -65 dB THD in nano-scale CMOS technology」主題。共同形成了獨特的指紋。

引用此