0.5 μm CMOS device design and characterization

H. I. Hanafi*, M. R. Wordeman, L. K. Wang, Y. Taur, J. Y.C. Sun, R. H. Dennard, D. S. Zicherman, M. D. Rodriguez, N. Haddad, A. Edenfeld, M. Polavarapu

*Corresponding author for this work

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

The design and characterization of a high performance 0.5 μm channel CMOS is described. The design features thin epi with retrograded n-well, an n+polysilicon gate electrode, 12.5 nm gate oxide, shallow source/drain diffusions, and thin self-aligned titanium silicides. To control channel hot electron degradation effects in the NFET device with 3.3V power supply, different S/D junctions with graded profiles are investigated. The n-well doping profile is adjusted to provide adequate short channel threshold control and punch-through immunity in the buried channel PFET. In this paper, measured device characteristics will be discussed. Stage delays of unloaded inverter ring oscillators down to 90 pS are presented. Circuit performance sensitivities to a variety of parameters such as channel length. power supply and series resistance are also shown.

原文English
主出版物標題ESSDERC 1987 - 17th European Solid State Device Research Conference
發行者IEEE Computer Society
頁面91-94
頁數4
ISBN(電子)0444704779
ISBN(列印)9780444704771
出版狀態Published - 1987
事件17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy
持續時間: 14 九月 198717 九月 1987

出版系列

名字European Solid-State Device Research Conference
ISSN(列印)1930-8876

Conference

Conference17th European Solid State Device Research Conference, ESSDERC 1987
國家Italy
城市Bologna
期間14/09/8717/09/87

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