0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS

Po-Tsang Huang, Shu Lin Lai, Ching Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang

研究成果: Conference contribution同行評審

8 引文 斯高帕斯(Scopus)

摘要

In this paper, a 256×40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the Ion/Ioff difference of the dynamic circuitry. To further improve energy efficiency, don't-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.

原文English
主出版物標題Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
發行者Institute of Electrical and Electronics Engineers Inc.
頁面129-132
頁數4
ISBN(電子)9781479940905
DOIs
出版狀態Published - 13 一月 2015
事件2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan
持續時間: 10 十一月 201412 十一月 2014

出版系列

名字Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
國家Taiwan
城市Kaohsiung
期間10/11/1412/11/14

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