0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications

Bing-Yue Tsui*, Chia Pin Lin, Chih Feng Huang, Yi Hsuan Xiao

*Corresponding author for this work

研究成果: Conference contribution同行評審

12 引文 斯高帕斯(Scopus)

摘要

Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 μm channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.

原文English
主出版物標題IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
頁面911-914
頁數4
DOIs
出版狀態Published - 1 十二月 2005
事件IEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States
持續時間: 5 十二月 20057 十二月 2005

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2005
ISSN(列印)0163-1918

Conference

ConferenceIEEE International Electron Devices Meeting, 2005 IEDM
國家United States
城市Washington, DC, MD
期間5/12/057/12/05

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