0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications

Bing-Yue Tsui; Chia Pin Lin; Chih Feng Huang; Yi Hsuan Xiao

doi:10.1109/IEDM.2005.1609507

0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications

Bing-Yue Tsui^*, Chia Pin Lin, Chih Feng Huang, Yi Hsuan Xiao

^*Corresponding author for this work

電子工程學系

研究成果: Conference contribution › 同行評審

12 引文斯高帕斯（Scopus）

摘要

Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 μm channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.

原文	English
主出版物標題	IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
頁面	911-914
頁數	4
DOIs	https://doi.org/10.1109/IEDM.2005.1609507
出版狀態	Published - 1 十二月 2005
事件	IEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States 持續時間: 5 十二月 2005 → 7 十二月 2005

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
卷	2005
ISSN（列印）	0163-1918

Conference

Conference	IEEE International Electron Devices Meeting, 2005 IEDM
國家	United States
城市	Washington, DC, MD
期間	5/12/05 → 7/12/05

存取文件

10.1109/IEDM.2005.1609507

指紋深入研究「0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications」主題。共同形成了獨特的指紋。

引用此

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title = "0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications",

abstract = "Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 μm channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.",

author = "Bing-Yue Tsui and Lin, {Chia Pin} and Huang, {Chih Feng} and Xiao, {Yi Hsuan}",

year = "2005",

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Tsui, B-Y, Lin, CP, Huang, CF & Xiao, YH 2005, 0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications. 於 IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest., 1609507, Technical Digest - International Electron Devices Meeting, IEDM, 卷 2005, 頁 911-914, IEEE International Electron Devices Meeting, 2005 IEDM, Washington, DC, MD, United States, 5/12/05. https://doi.org/10.1109/IEDM.2005.1609507

0.1μm poly-Si thin film transistors for system-on-panel (SoP) applications. / Tsui, Bing-Yue; Lin, Chia Pin; Huang, Chih Feng; Xiao, Yi Hsuan.

IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. 2005. p. 911-914 1609507 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2005).

研究成果: Conference contribution › 同行評審

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AB - Thin active layer, fully-silicided source/drain (S/D), modified Schottky barrier, high dielectric constant (high-k) gate dielectric, and metal gate technologies are integrated to realize high performance TFTs. Devices with 0.1 μm channel length were fabricated successfully. Low threshold voltage, low subthreshold swing, high effective mobility, low S/D resistance, high on/off current ratio, and good control of threshold voltage are demonstrated.

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