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研究成果

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Article
2020

Characteristics of Poly-Si Junctionless FinFETs with HfZrO Using Forming Gas Annealing

Chung, S. T., Lee, Y. J. & Chao, T. S., 1 一月 2020, 於 : IEEE Transactions on Nanotechnology. 19, p. 390-396 7 p., 9091928.

研究成果: Article

Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., 二月 2020, 於 : IEEE Transactions on Electron Devices. 67, 2, p. 711-716 6 p., 8951114.

研究成果: Article

2 引文 斯高帕斯(Scopus)

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Sung, P. J., Su, C. J., Lo, S. H., Hsueh, F. K., Lu, D. D., Lee, Y. J. & Chao, T. S., 1 一月 2020, 於 : IEEE Journal of the Electron Devices Society. 8, p. 474-480 7 p., 9063644.

研究成果: Article

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Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters

Sung, P-J., Chang, S-W., Kao, K-H., Wu, C-T., Su, C-J., Cho, T-C., Hsueh, F-K., Lee, W-H., Lee, Y-J. & Chao, T-S., 23 七月 2020, 於 : Ieee Transactions On Electron Devices. 67, 9, p. 3504-3509 6 p.

研究成果: Article

Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs

Shen, C. H., Chen, W. Y., Lee, S. Y., Kuo, P. Y. & Chao, T. S., 1 一月 2020, 於 : IEEE Transactions on Nanotechnology. 19, p. 322-327 6 p., 9044627.

研究成果: Article

2019

Experimental Demonstration of Stacked Gate-All-Around Poly-Si Nanowires Negative Capacitance FETs with Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process

Lee, S. Y., Chen, H. W., Shen, C. H., Kuo, P. Y., Chung, C. C., Huang, Y. E., Chen, H. Y. & Chao, T. S., 十一月 2019, 於 : IEEE Electron Device Letters. 40, 11, p. 1708-1711 4 p., 8835096.

研究成果: Article

4 引文 斯高帕斯(Scopus)
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1 引文 斯高帕斯(Scopus)
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2018
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2 引文 斯高帕斯(Scopus)

Junctionless FETs with a Fin Body for Multi-V TH and Dynamic Threshold Operation

Kumar, M. P. V., Lin, J. Y., Kao, K. H. & Chao, T-S., 1 八月 2018, 於 : IEEE Transactions on Electron Devices. 65, 8, p. 3535-3542 8 p., 8399532.

研究成果: Article

4 引文 斯高帕斯(Scopus)
11 引文 斯高帕斯(Scopus)

Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs with RTA-Improved Crystallinity

Shen, C. H., Kuo, P. Y., Chung, C. C., Lee, S. Y. & Chao, T-S., 1 四月 2018, 於 : IEEE Electron Device Letters. 39, 4, p. 512-515 4 p.

研究成果: Article

4 引文 斯高帕斯(Scopus)

Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation with Different Body Doping Concentrations

Lin, J. Y., Tsai, C. Y., Shen, C. H., Chung, C. C., Kumar, M. P. V. & Chao, T-S., 1 九月 2018, 於 : IEEE Electron Device Letters. 39, 9, p. 1326-1329 4 p., 8417437.

研究成果: Article

Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chung, C. C. C., Shen, C. H., Lin, J. Y., Chin, C. C. & Chao, T-S., 1 二月 2018, 於 : IEEE Transactions on Electron Devices. 65, 2, p. 756-762 7 p., 8233410.

研究成果: Article

12 引文 斯高帕斯(Scopus)
2017

Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 1 七月 2017, 於 : IEEE Transactions on Electron Devices. 64, 7, p. 2992-2998 7 p., 7934337.

研究成果: Article

2 引文 斯高帕斯(Scopus)

High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique

Hsieh, D. R., Kuo, P. Y., Lin, J. Y., Chen, Y. H., Chang, T. S. & Chao, T-S., 9 一月 2017, 於 : Semiconductor Science and Technology. 32, 2, 025004.

研究成果: Article

2 引文 斯高帕斯(Scopus)

High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications

Sung, P. J., Cho, T. C., Hou, F. J., Hsueh, F. K., Chung, S. T., Lee, Y. J., Current, M. I. & Chao, T-S., 1 五月 2017, 於 : IEEE Transactions on Electron Devices. 64, 5, p. 2054-2060 7 p., 7885526.

研究成果: Article

3 引文 斯高帕斯(Scopus)

Improving the Electrical Performance of a Quantum Well FET with a Shell Doping Profile by Heterojunction Optimization

Kumar, M. P. V., Hu, C. Y., Walke, A. M., Kao, K. H. & Chao, T-S., 1 九月 2017, 於 : IEEE Transactions on Electron Devices. 64, 9, p. 3563-3568 6 p., 7990547.

研究成果: Article

3 引文 斯高帕斯(Scopus)
2016

High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 1 十一月 2016, 於 : IEEE Transactions on Electron Devices. 63, 11, p. 4179-4184 6 p., 7582399.

研究成果: Article

8 引文 斯高帕斯(Scopus)

Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

Lin, J. Y., Kuo, P. Y., Lin, K. L., Chin, C. C. & Chao, T-S., 1 十二月 2016, 於 : IEEE Transactions on Electron Devices. 63, 12, p. 4998-5003 6 p., 7676340.

研究成果: Article

13 引文 斯高帕斯(Scopus)
17 引文 斯高帕斯(Scopus)
2015
10 引文 斯高帕斯(Scopus)

Impact of Crystallization Method on Poly-Si Tunnel FETs

Chen, Y. H., Ma, W. C. Y., Lin, J. Y., Lin, C. Y., Hsu, P. Y., Huang, C. Y. & Chao, T-S., 1 十月 2015, 於 : IEEE Electron Device Letters. 36, 10, p. 1060-1062 3 p., 7194770.

研究成果: Article

9 引文 斯高帕斯(Scopus)

Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs

Kumar, M. P. V., Hu, C. Y., Kao, K. H., Lee, Y. J. & Chao, T-S., 7 九月 2015, 於 : IEEE Transactions on Electron Devices. 62, 11, p. 3541-3546 6 p., 7244201.

研究成果: Article

20 引文 斯高帕斯(Scopus)

Switching characteristics in Cu:SiO2 by chemical soak methods for resistive random access memory (ReRAM)

Chin, F. T., Lin, Y. H., Yang, W. L., Liao, C. H., Lin, L. M., Hsiao, Y. P. & Chao, T-S., 1 一月 2015, 於 : Solid-State Electronics. 103, p. 190-194 5 p.

研究成果: Article

7 引文 斯高帕斯(Scopus)
2014

Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application

Chin, F. T., Lin, Y. H., You, H. C., Yang, W. L., Lin, L. M., Hsiao, Y. P., Ko, C. M. & Chao, T-S., 1 一月 2014, 於 : Nanoscale Research Letters. 9, 1

研究成果: Article

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9 引文 斯高帕斯(Scopus)

Characterization of ultra-thin Ni silicide film by two-step low temperature microwave anneal

Wu, C. T., Lee, Y. J., Hsueh, F. K., Sung, P. J., Cho, T. C., Current, M. I. & Chao, T-S., 1 一月 2014, 於 : ECS Journal of Solid State Science and Technology. 3, 5

研究成果: Article

1 引文 斯高帕斯(Scopus)

Effect of sensing film thickness on sensing characteristics of dual-gate poly-si ion-sensitive field-effect-transistors

Yen, L. C., Tang, M. T., Tan, C. Y., Pan, T. M. & Chao, T-S., 1 十二月 2014, 於 : IEEE Electron Device Letters. 35, 12, p. 1302-1304 3 p., 6954697.

研究成果: Article

5 引文 斯高帕斯(Scopus)

High-performance GAA sidewall-damascened sub-10-nm in situ n+-doped poly-Si NWs channels junctionless FETs

Kuo, P. Y., Lu, Y. H. & Chao, T-S., 1 十一月 2014, 於 : IEEE Transactions on Electron Devices. 61, 11, p. 3821-3826 6 p., 6897955.

研究成果: Article

18 引文 斯高帕斯(Scopus)

Improvement in pH sensitivity of low-temperature polycrystalline-silicon thin-film transistor sensors using H2 sintering

Yen, L. C., Tang, M. T., Chang, F. Y., Pan, T. M., Chao, T-S. & Lee, C. H., 25 二月 2014, 於 : Sensors (Switzerland). 14, 3, p. 3825-3832 8 p.

研究成果: Article

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5 引文 斯高帕斯(Scopus)

Ion-bombarded and plasma-passivated charge storage layer for SONOS-type nonvolatile memory

Liu, S. H., Wu, C. C., Yang, W. L., Lin, Y. H. & Chao, T-S., 1 一月 2014, 於 : IEEE Transactions on Electron Devices. 61, 9, p. 3179-3185 7 p., 6872548.

研究成果: Article

2 引文 斯高帕斯(Scopus)
2013

Al-SiO2-Y2O3-SiO2-poly-si thin-film transistor nonvolatile memory incorporating a Y2O 3 charge trapping layer

Pan, T. M., Yen, L. C., Mondal, S., Lo, C. T. & Chao, T-S., 26 七月 2013, 於 : ECS Solid State Letters. 2, 10

研究成果: Article

2 引文 斯高帕斯(Scopus)

Channel thickness effect on high-frequency performance of poly-Si thin-film transistors

Chen, K. M., Tsai, T. I., Lin, T. Y., Lin, H-C., Chao, T-S., Huang, G. W. & Huang, T. Y., 12 七月 2013, 於 : IEEE Electron Device Letters. 34, 8, p. 1020-1022 3 p., 6553156.

研究成果: Article

10 引文 斯高帕斯(Scopus)

Enhancement of open-circuit voltage using CF 4 Plasma treatment on nitric acid oxides

Lin, J. W., Wu, C. H., Wu, S. W., Hseih, W. P., Du, C. H. & Chao, T-S., 7 五月 2013, 於 : IEEE Electron Device Letters. 34, 5, p. 665-667 3 p., 6495702.

研究成果: Article

High-performance double-layer nickel Nanocrystal memory by ion bombardment technique

Liu, S. H., Yang, W. L., Lin, Y. H., Wu, C. C. & Chao, T-S., 4 十月 2013, 於 : IEEE Transactions on Electron Devices. 60, 10, p. 3393-3399 7 p., 6605590.

研究成果: Article

5 引文 斯高帕斯(Scopus)

High-performance polyimide-based ReRAM for nonvolatile memory application

Liu, S. H., Yang, W. L., Wu, C. C., Chao, T-S., Ye, M. R., Su, Y. Y., Wang, P. Y. & Tsai, M. J., 1 一月 2013, 於 : IEEE Electron Device Letters. 34, 1, p. 123-125 3 p., 6365747.

研究成果: Article

16 引文 斯高帕斯(Scopus)

High-κEu2O3 and Y2O3 poly-Si thin-film transistor nonvolatile memory devices

Pan, T. M., Yen, L. C., Huang, S. H., Lo, C. T. & Chao, T-S., 15 七月 2013, 於 : IEEE Transactions on Electron Devices. 60, 7, p. 2251-2255 5 p., 6523940.

研究成果: Article

5 引文 斯高帕斯(Scopus)

Impacts of multiple strain-gate engineering on a zero-temperature- coefficient point

Chang, T. S., Lu, T. Y. & Chao, T-S., 5 四月 2013, 於 : IEEE Electron Device Letters. 34, 4, p. 481-486 6 p., 6484132.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Improved rear-side passivation by atomic layer deposition A 2 O 3 /SiN x stack layers for high V OC industrial p-type silicon solar cells

Lin, J. W., Chen, Y. Y., Gan, J. Y., Hseih, W. P., Du, C. H. & Chao, T-S., 3 九月 2013, 於 : IEEE Electron Device Letters. 34, 9, p. 1163-1165 3 p., 6558507.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Low-temperature polycrystalline-silicon tunneling thin-film transistors with MILC

Chen, Y. H., Yen, L. C., Chang, T. S., Chiang, T. Y., Kuo, P. Y. & Chao, T-S., 7 八月 2013, 於 : IEEE Electron Device Letters. 34, 8, p. 1017-1019 3 p., 6544264.

研究成果: Article

16 引文 斯高帕斯(Scopus)

Microwave annealing of phosphorus and cluster carbon implanted (100) and (110) Si

Cho, T. C., Lu, Y. L., Yao, J. Y., Lee, Y. J., Sekar, K., Tokoro, N., Onoda, H., Krull, W., Current, M. I. & Chao, T-S., 15 十一月 2013, 於 : ECS Journal of Solid State Science and Technology. 2, 7

研究成果: Article

2 引文 斯高帕斯(Scopus)

Novel ion bombardment technique for doping limited Cu source in SiO x-based nonvolatile switching layer

Liu, S. H., Yang, W. L., Lin, Y. H., Wu, C. C. & Chao, T-S., 23 九月 2013, 於 : IEEE Electron Device Letters. 34, 11, p. 1388-1390 3 p., 6603277.

研究成果: Article

11 引文 斯高帕斯(Scopus)
2012

A novel ion-bombarded and plasma-passivated charge storage layer for SONOS-type nonvolatile memory

Liu, S. H., Yang, W. L., Wu, C. C. & Chao, T-S., 29 八月 2012, 於 : IEEE Electron Device Letters. 33, 10, p. 1393-1395 3 p., 6280616.

研究成果: Article

9 引文 斯高帕斯(Scopus)

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu 2O 3 gate dielectrics

Yen, L. C., Hu, C. W., Chiang, T. Y., Chao, T-S. & Pan, T. M., 23 四月 2012, 於 : Applied Physics Letters. 100, 17, 173509.

研究成果: Article

19 引文 斯高帕斯(Scopus)

High-performance poly-si thin-film transistors with L-fin channels

Lu, Y. H., Kuo, P. Y., Lin, J. W., Wu, Y. H., Chen, Y. H. & Chao, T-S., 1 二月 2012, 於 : IEEE Electron Device Letters. 33, 2, p. 215-217 3 p., 6095584.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Hydrogen instability induced by postannealing on poly-Si TFTs

Liao, C. C., Lin, M. C. & Chao, T-S., 24 四月 2012, 於 : IEEE Transactions on Electron Devices. 59, 6, p. 1807-1809 3 p., 6185651.

研究成果: Article

2 引文 斯高帕斯(Scopus)

Impacts of the underlying insulating layers on the MILC growth length and electrical characteristics

Liao, C. C., Lin, M. C., Liu, S. X. & Chao, T-S., 1 二月 2012, 於 : IEEE Electron Device Letters. 33, 2, p. 239-241 3 p., 6101550.

研究成果: Article

1 引文 斯高帕斯(Scopus)

Low-operating-voltage ultrathin junctionless poly-si thin-film transistor technology for RF applications

Tsai, T. I., Chen, K. M., Lin, H-C., Lin, T. Y., Su, C. J., Chao, T-S. & Huang, T. Y., 21 九月 2012, 於 : IEEE Electron Device Letters. 33, 11, p. 1565-1567 3 p., 6302168.

研究成果: Article

4 引文 斯高帕斯(Scopus)
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7 引文 斯高帕斯(Scopus)