每年專案
個人檔案
研究專長
矽奈米電子、半導體元件物理、元件模型及設計
經歷
2003/08~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, University of California, Berkeley
外部位置
指紋
查看啟用 Pin Su 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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網路
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專案
研究成果
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A New 8T Hybrid Nonvolatile SRAM with Ferroelectric FET
You, W. X., Su, P. & Hu, C., 7 二月 2020, 於 : IEEE Journal of the Electron Devices Society. 8, 1, p. 171-175 5 p., 8986584.研究成果: Article › 同行評審
開啟存取 -
Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
Huang, S. E., Lin, S. H. & Su, P., 14 一月 2020, 於 : IEEE Journal of the Electron Devices Society. 8, p. 105-109 5 p., 8959139.研究成果: Article › 同行評審
開啟存取 -
Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers
Lin, C. C., Wu, Y. J., You, W. X. & Su, P., 八月 2020, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., p. 62-63 2 p. 9203647. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).研究成果: Conference contribution › 同行評審
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Simulation and Design of Ultra-Thin-Body FeFET NVMs Considering Minor Loop Operation
Wu, F. C., You, W. X. & Su, P., 八月 2020, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., p. 78-79 2 p. 9203737. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).研究成果: Conference contribution › 同行評審
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Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
Liu, Y. S. & Su, P., 三月 2020, 於 : IEEE Electron Device Letters. 41, 3, p. 369-372 4 p., 8962180.研究成果: Article › 同行評審