每年專案
個人檔案
研究專長
電子設計自動化、生物晶片設計自動化、微處理器設計、矽智財與系統單晶片設計
經歷
1998/07~2003/10 創意電子公司經理
2003/11~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, National Chiao Tung University
外部位置
指紋
查看啟用 Juinn-Dar Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 12 類似的個人檔案
網路
國家層面的近期外部共同作業。通過按一下圓點深入探索詳細資料。
專案
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智慧終端系統晶片研發與新創事業計畫-子計畫三：智慧終端晶片設計與驗證方法論之開發(1/2)
1/05/20 → 30/04/21
研究計畫: Ministry of Science and Technology
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智慧終端系統晶片研發與新創事業計畫-子計畫三：智慧終端晶片設計與驗證方法論之開發(2/2)
1/05/19 → 30/04/20
研究計畫: Ministry of Science and Technology
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智慧終端系統晶片研發與新創事業計畫-子計畫三：智慧終端晶片設計與驗證方法論之開發(1/2)
1/05/18 → 30/04/19
研究計畫: Ministry of Science and Technology
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以資料分析為導向之新型態電子設計自動化研究-子計畫一：採用資料分析法則之可重組態單電子電晶體陣列自動合成技術(2/2)
1/05/15 → 30/04/16
研究計畫: Ministry of Science and Technology
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針對大型微流體生物晶片之設計自動化技術研發-子計畫四：應用於微流體生物晶片上之生化反應樣本製備流程(2/2)
1/05/15 → 30/04/16
研究計畫: Ministry of Science and Technology
研究成果
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A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization
Lu, Y., Wu, Y. L. & Huang, J. D., 八月 2020, Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020. Institute of Electrical and Electronics Engineers Inc., p. 198-202 5 p. 9073835. (Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020).研究成果: Conference contribution › 同行評審
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Storage-Aware Algorithms for Dilution and Mixture Preparation with Flow-Based Lab-on-Chip
Bhattacharjee, S., Wille, R., Huang, J-D. & Bhattacharya, B. B., 四月 2020, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.研究成果: Article › 同行評審
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Design automation for dilution of a fluid using programmable microfluidic device-based biochips
Gupta, A., Huang, J-D., Yamashita, S. & Roy, S., 1 二月 2019, 於: ACM Transactions on Design Automation of Electronic Systems. 24, 2, 3306492.研究成果: Article › 同行評審
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Forecast-based sample preparation algorithm for unbalanced splitting correction on DMFBs
Song, L. Y., Chen, Y. L., Lei, Y. C. & Huang, J. D., 十一月 2019, Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019. Institute of Electrical and Electronics Engineers Inc., p. 422-428 7 p. 8988712. (Proceedings - 2019 IEEE International Conference on Computer Design, ICCD 2019).研究成果: Conference contribution › 同行評審
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Reactant minimization for multi-target sample preparation on digital microfluidic biochips using network flow models
Fan, K. Y., Yamashita, S. & Huang, J. D., 四月 2019, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8742025. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).研究成果: Conference contribution › 同行評審