每年專案
個人檔案
研究專長
類比數位混合式積體電路
經歷
1992 - 迄今，教授，國立交通大學電子工程學系
1988/02 - 1992/2，Member of Technical Staff，美國惠普公司
教育/學術資格
PhD, Stanford University
外部位置
指紋
查看啟用 J-T Wu 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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網路
國家層面的近期外部共同作業。通過按一下圓點深入探索詳細資料。
專案
研究成果
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An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
Swindlehurst, E., Jensen, H., Petrie, A., Song, Y., Kuan, Y. C., Qu, Y., Chang, M. C. F., Wu, J-T. & Chiang, S. H. W., 2021, (Accepted/In press) 於: IEEE Journal of Solid-State Circuits.研究成果: Article › 同行評審
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A 1-V 175-μ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
Liao, S. H. & Wu, J-T., 九月 2019, 於: IEEE Journal of Solid-State Circuits. 54, 9, p. 2523-2531 9 p., 8765753.研究成果: Article › 同行評審
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An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC with Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
Swindlehurst, E., Jensen, H., Petrie, A., Song, Y., Kuan, Y. C., Chang, M. C. F., Wu, J-T. & Chiang, S. H. W., 九月 2019, 於: IEEE Solid-State Circuits Letters. 2, 9, p. 83-86 4 p., 8877924.研究成果: Article › 同行評審
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An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC with Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
Swindlehurst, E., Jensen, H., Petrie, A., Song, Y., Kuan, Y. C., Chang, M. C. F., Wu, J. T. & Chiang, S. H. W., 九月 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 83-86 4 p. 8902621. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).研究成果: Conference contribution › 同行評審
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A 1 v 175 μw 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques
Liao, S. H. & Wu, J-T., 9 五月 2018, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p. (2018 IEEE Custom Integrated Circuits Conference, CICC 2018).研究成果: Conference contribution › 同行評審