周承翰

約聘助理研究員

國立交通大學

https://orcid.org/0000-0003-2919-2539

每年研究成果

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5 Article
2 Conference contribution
1 Comment/debate

8結果

2020
Improving Interface State Density of TiN/HfO₂/IL Gate Stack on Si_0.5Ge_0.5by Optimization of Post Metallization Annealing and Oxygen Pressure
Lee, M. C., Lee, W. L., Yu, C. Y., Lin, H. J., Liu, H. H., Zhang, J. L., Wang, S. Y., Chou, C. H., Luo, G. L. & Chien, C. H., 八月 2020, 2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020. Institute of Electrical and Electronics Engineers Inc., p. 102-103 2 p. 9203589. (2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020).
研究成果: Conference contribution › 同行評審
2018
Incorporating yttrium into a GeO interfacial layer with HfO₂-based gate stack on Ge
Chou, C. H., Lu, Y. H., Tsai, Y. H., Shih, A. S., Yeh, W. K. & Chien, C. H., 19 一月 2018, 於: ECS Journal of Solid State Science and Technology. 7, 2, p. N15-N19 5 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2017
Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping
Chou, C. H., Tsai, Y. H., Hsu, C. C., Jau, Y. H., Lin, Y. H., Yeh, W. K. & Chien, C. H., 1 五月 2017, 於: IEEE Transactions on Electron Devices. 64, 5, p. 2314-2320 7 p., 7885604.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
2016
Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs
Hsu, C. C., Chi, W. C., Tsai, Y. H., Chou, C. H., Chen, C. W., Chien, H. P., Chuang, S. S., Luo, G. L., Lee, Y. J. & Chien, C. H., 1 七月 2016, 於: IEEE Transactions on Electron Devices. 63, 7, p. 2714-2721 8 p., 7484321.
研究成果: Article › 同行評審
4 引文斯高帕斯（Scopus）
Low-leakage tetragonal ZrO ₂ (EOT < 1 nm) with in situ plasma interfacial passivation on germanium
Chou, C. H., Chang, H. H., Hsu, C. C., Yeh, W. K. & Chien, C. H., 1 二月 2016, 於: IEEE Electron Device Letters. 37, 2, p. 138-141 4 p., 7358074.
研究成果: Article › 同行評審
11 引文斯高帕斯（Scopus）
2015
3D-TCAD simulation study of the novel T-FinFET structure for sub-14nm metal-oxide-semiconductor field-effect transistor
Chou, C. H., Hsu, C. C., Chung, S. S. & Chien, C. H., 24 九月 2015, 2015 Silicon Nanoelectronics Workshop, SNW 2015. Institute of Electrical and Electronics Engineers Inc., 7275311. (2015 Silicon Nanoelectronics Workshop, SNW 2015).
研究成果: Conference contribution › 同行評審
2 引文斯高帕斯（Scopus）
Erratum: Fabricating a n⁺-Ge contact with ultralow specific contact resistivity by introducing a PtGe alloy as a contact metal(Applied Physics Letters (2015) 107(113503))
Hsu, C. C., Chou, C. H., Wang, S. Y., Chi, W. C., Chien, C. H. & Luo, G. L., 7 十二月 2015, 於: Applied Physics Letters. 107, 23, 239901.
研究成果: Comment/debate
Fabricating a n⁺-Ge contact with ultralow specific contact resistivity by introducing a PtGe alloy as a contact metal
Hsu, C. C., Chou, C. H., Wang, S. Y., Chi, W. C., Chien, C. H. & Luo, G. L., 14 九月 2015, 於: Applied Physics Letters. 107, 11, 113503.
研究成果: Article › 同行評審
4 引文斯高帕斯（Scopus）

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