Yield and performance issues in fault-tolerant WSI array architectures

Yung Yuan Chen*, Sau-Gee Chen, Jiann Cherng Lee

*Corresponding author for this work

Research output: Contribution to journalConference article

3 Scopus citations

Abstract

In this paper, a simple but efficient reconfiguration algorithm and placement algorithm are proposed to enhance the manufacturing yield of WSI array processors at low performance degradation. The low performance degradation is significant for high-performance WSI arrays. The objective of our reconfiguration strategy is to achieve better utilization of good spares, while also ensuring that the restructured inter-PE communication links do not become so long as to significantly degrade the performance. Monte Carlo simulation is performed to estimate the array yield and to obtain the performance degradation probability distribution for fault patterns with both PE and switch faults. The simulations conducted indicate that the computational time of the algorithms is quite low, therefore the proposed scheme may also be very suitable for certain run-time fault tolerance.

Original languageEnglish
Pages (from-to)318-328
Number of pages11
JournalProceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 7th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 18 Jan 199520 Jan 1995

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