Wide duty cycle range synchronous mirror delay designs

D. Sheng*, C. C. Chung, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A wide duty cycle range and small static phase error synchronous mirror delay (SMD) for system-on-chip (SoC) applications is presented. The conventional SMD accepts only the pulsed clock signal and has large static phase error. The proposed SMD uses the edge-trigger mirror delay cell to enlarge the input duty cycle range and the blocking edge-trigger scheme to ensure functionality and performance. Moreover, phase error can be reduced by the proposed delay-matching structure and fine-tuning delay line with a high-resolution delay cell. Simulation results of SMD show that the input clock duty cycle range is from 20 to 80 and the worst static phase error under different process, voltage, and temperature conditions can achieve 18ps at 400MHz.

Original languageEnglish
Pages (from-to)338-340
Number of pages3
JournalElectronics Letters
Volume46
Issue number5
DOIs
StatePublished - 19 Mar 2010

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