In this paper, we present a new address translation and memory protection model to manage the wide 64-bit virtual address space, called the segment-based translation and protection (SBTP) model. It partitions a 64-bit virtual address space into 232 segments with equal size of 232 bytes. The SBTP model maintains a segment table to record used segments for each process. As a result of caching the per-process basis segment table on a designed memory cache, called the segment look-aside buffer (SLB), the virtual address translation time and protection rights verification time can be reduced. Furthermore, by separating the hardware mechanisms of address translation and protection, mapping information stored in the translation look-aside buffer (TLB) can be shared by all the processes and need not be flushed on each context switch. Thus, the cost of context switching compared with that conventional architectures is greatly reduced. Simulation results show that the proposed memory architecture effectively improves the performance of wide virtual address translation and memory protection for single address space operating systems.
|Number of pages||11|
|Journal||Proceedings of the National Science Council, Republic of China, Part A: Physical Science and Engineering|
|State||Published - 1 Sep 1998|